ASIC North Chooses North Carolina for New Design Center
Williston, VT (PRWEB) July 02, 2011
ASIC North, Inc. (http://www.asicnorth.com), one of the fastest growing design service companies in the United States, is announcing plans to expand their operations into the Research Triangle Park area of North Carolina. The company is currently hiring experienced engineers and will be conducting multiple job fairs in the region, with the first scheduled for July 12th through 14th.
“In response to increasing demand, ASIC North is further expanding its operations,” said President Mike Slattery. “In today’s uncertain economy, high tech companies are turning to design service providers to extend their existing design teams and accelerate product development schedules.”
In its 12th year in business, ASIC North offers a broad range of VLSI design services from digital design to analog-mixed signal design to hardware-based characterization. Furthermore, ASIC North can engage with several different business models to meet project requirements. This flexibility enables the customer to find the right solution that meets their specific needs.
“We have collaborated with ASIC North for over four years on complex mixed-signal designs for many IBM custom logic programs; ” said John Chickanosky, Memory and Protocol Manager, IBM. “We appreciate the added flexibility and options this expansion enables.”
“The Research Triangle and the City of Raleigh are excited to have a company like ASIC North locate to our community. Their commitment is another example of how a talented workforce can attract industry”, said James Sauls, Director of Raleigh Economic Development.
“We’re delighted to become part of the business community in one of the premier research areas of the world,” said Slattery. “The Raleigh-Durham area is an ideal location for our next design center. Our research shows the technology industry located in the region provides the business opportunities and skilled workforce required to fuel this latest expansion. We believe our new design center in North Carolina is strategic to the future success of ASIC North.”
About ASIC North, Inc.
ASIC North (http://www.asicnorth.com) is a leading VLSI design service provider specializing in enabling integrated device manufacturers (IDMs) and fabless semiconductor companies. With vast experience in CMOS circuit design, an analog mixed-signal IP library, ASIC design capabilities, and characterization services, ASIC North has the ability to create a broad of range of semiconductor-based solutions. ASIC North has design centers in Williston, VT and Tempe, AZ.
For both introductory and advanced courses in VLSI design, this authoritative, comprehensive textbook is highly accessible to beginners, yet offers unparalleled breadth and depth for more experienced readers.
The Fourth Edition of CMOS VLSI Design: A Circuits and Systems perspective presents broad and in-depth coverage of the entire field of modern CMOS VLSI Design. The authors draw upon extensive industry and classroom experience to introduce today’s most advanced and effective chip design practices. They present extensively updated coverage of every key element of VLSI design, and illuminate the latest design challenges with 65 nm process examples. This book contains unsurpassed circuit-level coverage, as well as a rich set of problems and worked examples that provide deep practical insight to readers at all levels.
By Ahmed Abu-Hajar, Ph.D. This is part 6-A of lecture 1. You may visit www.digitavid.net to download a free evaluation version of the compelete software
By Ahmed Abu-Hajar, Ph.D. This is part 2 of lecture 1. you may visit www.digitavid.net to download free evaluation version of the compelete software
The word of Chip designing means building an integrated Chip, by integrating billions of transistors to achieve an application. An Application could be suiting a particular requirement like Microprocessor,Router,cell phone,etc. An Integrated circuit designed for a specific application is called as ASIC(Application Specific Integrated Circuits).
Todays ASIC Chips is prettly complex packed with larger chunk of transistors targetted to a specific manufacturing process for fabricating the integrated circuits, in a sub nanometer regime, involving lots and lots of challenges, like knowledge of various protocols, architectures, models, formats, standards, knowledge about CMOS logic, Digital Design concepts, taming the EDA tool for the various design requirement’s like area, timing, power, thermal, noise, routability, lithography aware, knowledge about Various variabilities like channel length, Vt, line width variations, lens abrreations, IR drop effects,inter-die, intra die-variations, effects, and various noise-effects like Package noise,EMI noise,power grid noise,cross-talk noise and ability to test and validate and know to model and characterize all these effects upfront in the design-phase,steps to increase yield to increase profitability curve, with short span of time-to market to minimize the risk and maximize the predictability and an modular approach to Success. Now let’s dwelve in to the “Art of Chip Designing”
Used lot of Technical Jargons, nothing to worry about we will get in there soon…Be with me promise you understand the Concepts behind Chip Desiging.
Before Designing a Chip? Need to Brain Storm
1. What market the Chip is targetted for?
2. What are the Protocols involved in the Chip?
3. What is going to be our Processor/Bus Architecutes?
4. what is the power/IR-drop/timing/Area/Yield/ targets and how to budget it in the Chip?
5. What is the process in which the Chip going to be manufactured?
7. what are the various third party IP’s/Memory requirements?
8. what is our Design flow and EDA tools and methodology involved?
9. What is the estimated Chip Cost?
10. Above all the bottom line of any business model is money, What will be our Profit model ,estimation of our ROI(Return of investment).
Analogy of Chip Design Architecture Vs Building Architecture
Why an Analogy with Building Architecture,It is just to understand the concepts of Chip desiging in a better way, as we are very familiar with Building Architecture, then it will be easy for us to map Chip Design architecture.
VLSI(Very large scale Integration) flow was evolved similar to the flow involved in Building Construction.Now let us dwelve in to the constuction flow to better understand the VLSI Chip design flow development.
When ever we start to construct a building, we will have an architecture, how the building should look like , the exterior looks and all, similar to that we will be designing an architecture in the chip-design, based on the requirement of the product, what the product is addressed for and whom to serve what needs, the so called specification, will having the modules.
Now lets go in to the implementation part of both the Building & Chip.
We at first come with the floorplan of the building, similarly we come with the floorplan of the Chip, Based on the connectivity/accessibility/vaasthu we place our rooms, similarly we have the constraints to place the blocks. Like we build the building with bricks, for Chip Design we have libraries, which are like pre-designed bricks, for a specific functionality.
Now let us try to understand the power-structure or electrical connectivity in our Building. Initially we have an Electrical plan for our building, where we have a requirement that all our electrical gadgets needs to get power. Similar to that we have a Chip power requirement, The required power is supplied through the power-pads, over a ring like topology to have a uniform distribution across all corners of the chip, and the supply has to reach all the standard-cells(bricks for Chip-Designing).,this is called as power-grid topology in the Chip-Design, now the requirement is how well we design our Power-grid, to reduce the IR-drop so that our standard-cells get proper power requirement.
I would not make justice, if I dont discuss about clock and clock-tree in the Chip-Design flow. We have synchronous way of designing and asynchronous way of designing(difficult to verify). Majority of chips follow Synchronous way of coding, for which Static Timing Analysis is possible. For the relevancy of the flops the clock to those flops should reach at the same time from the crystal, with in some skew targets with in the chip.In order to make this happen, a step called as clock-tree is performed after power-grid is created.
Let us try to visualize the concept behind Place & Route in Chip Design. We need to undergo lot of modelling concepts, to understand the process of Chip-Designing. To have a better understanding of this concept of place and route, let us assume a society where people who are speaking different languages are living , and let us visualize that people talking of the same languages are living in a community, then the communication is much easier , similar way in the chip-designing, the standard-cells who are having design relation-ships, are placed closer in the Placement flow this concept is called as regioning. Now with in the regioning, of the groups of the standard-cells, the cells which are really sharing data, has to placed close-by so that there timing is achieved and well optimized.This step is called placement, Connectivity across the standard-cells is called as routing, the challenge is having optimized or reduced wire-lengths.
Now let us try to try to understand the concept behind signal integrity in the Chip-Design , often called us SI Effect. As our process is shrinking day by day, and our silicon-realestate is costly, we try to accommodate more and more standard-cells in the limited area, so the cells are placed in very close proximity, so the switching of one can have an impact over the others behaviour, which can make the path to be faster or slower, this issue is called as signal-integrity. So similar way in our construction in order to maintain the integrity with in the house(neighbour free-zone), within the limited zone of modurality, we try to create fences, across buildings, similarly we can think of a concept called as Shielding, the high frequency signal net with the power-nets running across. We perform spacing across the buildings, similar way we can perform spacing across the nets, which are in close proximities.
In order to validate the silicon from the manufacturability issues, the concept in the Chip Desigining is Design for Test(DFT). One of the DFT techniques is scan-chain. To understand the concept of the scan-chain, we can visualize that we have a front-door entry and a back-door exit, and a person passes from the front-door and exits from the back-door exit of the building, that we are sure that there is no blocking within the rooms in the building, to make that person stuck , similar to this analogy the flip-flops are connected to-gether creating a scan-chain and test-input values are passed from the scan-chain input of the chip and expected data is visualized in the scan-chain output of the chip, then the assumption is the chip is free from manufacturability issues like stuck-at faults(stuck-at one or stuck at zeros).
Chennai, January 4, 2011: Delivering the keynote address, Thomas H Lee, Professor, Stanford University, said,”VLSI Design and embedded systems are core technologies that are behind the electronic products that we use widely today including cell phones, music players, and computers. There is a need to have discussions on the trend and future of this segment as these are the backbone of all electronics used widely today in various domains such as Communications, Consumer, Industrial, Automotive, Defense and Health Care. I strongly believe embedded to be the next big thing driven by the increasing pervasiveness of microprocessors in all walks of life.”
Speaking on VLSI Design from Indian academician perspective, Praveen Vishakantaiah, President, Intel India said, “With India projected to consume billion worth of embedded electronics by 2020 it is emerging as a market of focus and the future. The key challenge we face today is lack of research efforts and researches. This is critical as that is the pinnacle of the embedded and VLSI arena and fuels innovation. An encouraging sign is the increasing number of partnerships companies in this space are entering into with educational institutes for doing research programs and internships.”
Kamakoti, General Co-Chair, VLSI and Professor at Department of Computer Science and Engineering, IIT-Madras speaking on the general vision of VLSI Design Conference 2011 said, “One area of focus for the conference is to make students understand the phenomenal opportunity in the embedded and VLSI arena. And by listening to and seeing the innovations happening be inspired to take it to greater heights through their intelligence and effort. Realizing this importance, we have designed the conference with several complementary parts – full-day tutorials, research paper presentations, special sessions with invited embedded tutorials, hot topic presentations, keynote and banquet talks, and the industry and education forums.”
In his comments, Prof. Vishwani Agrawal of Auburn University, US and Member of VLSI committee, added, “VLSI Design 2011 will definitely add value to the industry by providing a platform for the experts to discuss the issues of this industry. After 13 years, we have organized the annual premier joint conference of India at Chennai as we foresee the city emerging as a potential hub for the industry”.
VLSI Design 2011 focuses on “Embedded products for emerging markets- Infrastructure, Energy & Automotive” as the key conference theme and will see more than 100 eminent global and Indian industry experts share trends, opportunities and challenges of India’s growing VLSI (Very Large Scale Integration) sector. Discussions and deliberations will focus on technology, manufacturing, markets, applications, finance and policy and a first-of-its-kind workshop on Reliability Aware System Design and Test (RASDAT) (Jan 6th & 7th). The 3 day conference will also include technical paper session on latest research and embedded tutorials. Industry presentation sessions, panel discussions and design contests and industrial exhibits to round off the program. Eminent speakers at the event include; Rahul Sarpeshkar (Associate Professor, MIT): Bioelectronics, Kaushik Roy (Professor, Purdue University): Post-Silicon technologies: Prospects and Perspectives, Anant Agarwal (CTO, Tilera and Professor, MIT): The Future of Multicore, Peter Kinget (Associate Professor, Columbia University): Designing Analog and RF Circuits in Nanoscale CMOS Technologies: Scale the Supply, Reduce the Area and Use Digital Gates, Rajeev Madhavan (CEO, Magma Design Automation): Real Men do Real Silicon, Leon Stok (VP, IBM): High-end Processor design in Advanced CMOS Technologies. The Conference covers the entire gamut of activities under the two folds of Semiconductor Industry – VLSI and Embedded systems
About VLSI Society of India/VLSI Conference: The mission of the society is to make India a significant force in VLSI field and to promote applications and research related to all aspects of VLSI in India. VSI holds workshops and short-courses through the year, in all parts of the country to bring together the industry, academia and mainly the students, on hot and emerging topics of VLSI and the related. VSI welcomes volunteers to get involved in such activities. VSI publishes the half-yearly technical journal VSI VISION. It also compiles softcopies of the proceedings of all workshops, short-courses and VDAT Symposium, which has hardcopy publication additionally. International Conference on VLSI Design and International Conference on Embedded Systems is the annual international event, that VSI is associated with and sponsors that attracts a wide spectrum of VLSI related professionals and academia.
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