Analog signal processing circuit blocks implemented in mixed-signal systems utilize more digital signal processing where the quality of the analog components can be reduced at the cost of digital system complexity. Discussing these design techniques from a circuit designer’s point of view, CMOS is an advanced guide to mixed-signal circuit design that will bring designers rapidly up to speed. This new edition features additional examples and more, smaller chapters to make the information more accessible to graduate students as well as professionals who want to improve their skills in this area.

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Linear Integrated Circuits – Professor Clark Tu-Cuong Nguyen
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Hardware designers are routinely challenged to increase functional density while shrinking the overall PCB footprint of each new design. One significant challenge is minimizing clock jitter through careful board design while meeting the design’s functional and space requirements. Since jitter is a measure of signal fidelity, it requires an understanding of diverse analog concepts, such as transmission line theory, interference, bandwidth, and noise, in order to manage their impact on performance. Among these, density impacts sensitivity to external noise and interference the most. Since noise and interference are everywhere and since multiple components share a common power supply, the power supply is a direct path for noise and interference to impact the jitter performance of each device. Therefore, achieving the lowest clocking jitter requires careful management of the power supply. Sensitivity to power supply is commonly referred to as power supply ripple rejection or power supply rejection ratio (PSRR). For jitter, ripple rejection is more appropriate.

2. Impact

The effect of power supply ripple on jitter is quite straightforward. Power supply influences the propagation delay by affecting both the switching voltage threshold of logic gates as well as the output resistance. As the switching voltage threshold is modulated, the time at which the output transitions is modulated because the input signal has a finite slope .

Varying output resistance affects the propagation delay of the CMOS gate through the parasitic RC filter. When combined, these two effects change the propagation delay through the CMOS gate. The effect is amplified as more gates are placed in series.

The degree of the impact is highly dependent on the “speed” of the transistors involved. By having a faster slope at the CMOS gate input, the impact from a changing threshold can be minimized. In addition, faster circuits require that capacitance be minimized in order to achieve small propagation delays; so, the delay variation due to supply variations can be minimized by making the routing capacitance as small as possible. However, there are trade-offs;the downside to faster circuits is power consumption. To make a faster edge, more current is required to charge the capacitors given a constant voltage.

3. Overcoming Supply Sensitivities

Common methods used to reduce supply sensitivity are supply filtering and minimizing circuit sensitivities.

3.1. Filtering

Power supply ripple rejection is often managed for an integrated circuit using both external and internal methods.Externally, board designers use active and passive filters to attenuate ripple and differential interfaces to reject common-mode ripple. Internally, architecture choices, linear regulators, and differential circuits are used to reduce circuit sensitivities to the power supply.

Direct filtering of the power supply can be achieved using passive filters or linear regulators. A common external filter solution relies upon a ferrite bead and discrete surface-mount ceramic capacitors With this approach, series resistance must be minimized to avoid reducing the supply voltage at the IC.

Unfortunately, the filtering is highly dependent on the series impedance (resistance plus reactance); so, ensure that the ferrite bead can handle the device current. Linear regulators can also filter supply noise by using the regulator as a high-pass filter. Often, these techniques are combined to provide filtering across the entire band of concern.

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Depending on the level of performance desired and the cost targets associated with a given design, one should consider the cost and power trade-offs associated with external filtering. Ferrite beads are much less expensive than active regulators and waste almost no power, but they cannot achieve the same level of filtering at low frequencies as that achieved by regulators. Consequently, pre-design evaluation of timing hardware should include power supply ripple rejection testing.

Differential circuits help reject power supply noise by allowing the supply interference to occur in the common mode and eliminating the interference by subtracting the common-mode signal. As the positive and negative legs are degraded by supply ripple, they accumulate the noise in common.

By subtracting these signals, the supply noise is rejected. A concern here is the receiver’s ability to reject commonmode noise. This is referred to as common-mode ripple rejection (CMRR). Just as in the CMOS gate, fast rise/fall times help.

External filtering may be necessary for designs that do not support differential signaling. Many timing devices with CMOS/TTL interfaces fail to account for power supply ripple. System designers should verify ripple rejection on the bench.

3.2. Circuit Choices

Architectural choices also play a role in ensuring good jitter performance when subjected to power supply ripple.Timing devices often rely on phase-locked loops (PLLs) to perform various functions, such as jitter filtering and frequency multiplication. One of the primary challenges in PLL design is associated with its voltage-controlled oscillator (VCO). To meet the frequency requirements for a variety of applications, it is often necessary to have a wide tuning range oscillator, but oscillator jitter is proportional to the noise at its control input (often its most sensitive port). To reduce the jitter, it is necessary to have a low-gain control input, but the lower limit for the gain is set by the range of frequencies required and the frequency impairments of the oscillator (e.g., process variation, temperature, strain, etc.) This gain limitation can be overcome with novel circuit techniques, such as those employed by Silicon Laboratories’ DSPLL™ technology. DSPLL utilizes a digitally-controlled, variable-gain oscillator; DSPLL can provide both a large tuning range and low gain, thereby minimizing its sensitivity during operation.

Furthermore, most timing integrated circuits operate from low supply voltages (less than 5 V). As the voltage is reduced with shrinking process geometries, the control port tuning range is limited as well. To achieve all of the output frequencies, the tuning port gain must be increased. Also, as the supply voltage is reduced, the tuning signal amplitude decreases relative to the noise (i.e., reduced SNR). Higher gain and reduced SNR yields poor jitter performance. It is critical to choose timing devices, such as those employing DSPLL™ by Silicon Labs, which have solved these problems.

DSPLL™ supports both low-voltage supplies and improved SNR by using a digital interface for its controlled oscillator. A digital interface allows the SNR to remain high and the gain to be set arbitrarily low regardless of the supply voltage level. The SNR remains high because the tuning range is not limited by the supply voltage. Other architecture choices also help: eliminating VCOs removes the concern over the tuning gain and interference altogether. Silicon Laboratories MultiSynth technology provides any-frequency synthesis simultaneously on multiple outputs using only a single VCO per IC. By employing only one VCO, Silicon Labs has increased functional density without increasing interference.

4. Measurement of Supply Sensitivity

Benchmarking the system performance can be as difficult as building in ripple rejection. Two common challenges are universally present. First, power supplies have low impedance in order to maintain constant voltage regardless of the load and, second, jitter/phase noise test equipment usually only supports “single-ended” analog signals instead of differential and/or rail-to-rail signals associated with high-performance timing circuits. To properly evaluate the jitter performance, accounting for the low impedance supply rails and the signaling requirements is necessary.

Having a low impedance network to analyze implies that high current will be necessary to achieve the desired ripple voltage (e.g., 100 mVpp), and high current signal sources are not common. To place a constant voltage ripple signal on a node that has a low impedance requires the ripple source to have a high drive strength. An easy way to achieve sufficient dc current for device operation and sufficient ac current for ripple generation is to source these requirements from separate supplies. This separation can be achieved by using a standard power supply and ac couple in parallel with a sinusoidal signal source (ripple source). The ripple source will need high impedance at dc to avoid sinking significant current from the power supply and potentially damaging the ripple source. Low impedance is also nebulous as a description since impedance is a function of frequency.

Consequently, the ripple source must be adjusted for each interference frequency to achieve a constant ripple voltage. The phase of the ripple signal is often ignored since it does not provide actionable data (i.e., the goal is to limit the magnitude of the ripple response; therefore, focus on the magnitude response). To overcome a single-ended analyzer input, use a differential amplifier or limiting amplifier. The phase noise (i.e.,jitter) is convoluted with amplitude noise and must be separated. A limiting amplifier rejects the common-mode interference so that a spectrum will only report the phase response.

Relative power is expressed in decibels (dB) relative to the output frequency (carrier) with units expressed as dBc(decibels relative to the carrier power). Because the limiting amplifier removes most of the amplitude noise and interference, it can be assumed that the measured side-band spurs can be attributed entirely to phase jitter. This allows a direct measurement of the RMS jitter induced by the ripple source. Equation 1 shows the relationship between side-band relative power and RMS jitter. The spurs are measured across a desired frequency range after setting the ripple voltage to a desired level.

(-59.

Equation 1. RMS Jitter Calculated for Phase-Induced Spurious Signals

4.1. Example

A common scenario to consider is the jitter resulting from 100 mVpp sinusoidal ripple across the 10 kHz to 3 MHz range. Such a comparison was made with Silicon Labs’ Si530 XO products and a competing product.

5. Conclusion

Power supply ripple rejection performance is dependent on the internal power supply filtering and architectural choices within timing ICs. Designers can evaluate timing ICs through a simple frequency sweep and compare devices for a constant ripple voltage. Such comparisons can help designers select the best device for their system,which is especially important when differences in performance are dramatic .

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Home Page > Technology > Evolution of Semiconductor Parameter Analyzers for Three Critical Types of Semiconductor Measurement – Part II

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Evolution of Semiconductor Parameter Analyzers for Three Critical Types of Semiconductor Measurement – Part II

By: Lee Stauffer
Posted: Jul 13, 2010

To replace traditional DC I-V techniques, various implementations of high-speed (i.e., pulsed) I-V techniques have been developed for applications such as characterizing high-k dielectrics and Silicon-On-Insulator (SOI) isothermal testing. When testing SOI devices with traditional DC I-V techniques, their insulating substrates cause them to retain the self-heat generated by the test signal, skewing their measured characteristics; testing with pulsed signals reduces this effect. Similar problems arise in the testing of high-k gate structures of CMOS devices, nanotechnology devices, solar cells, and many materials using advanced technologies.

Traditional High-Speed-Pulse/Measure Systems. Earlier high-speed-pulse/measure test systems typically involved an external pulse generator, a multi-channel oscilloscope, specially designed interconnect hardware, and software to integrate and control the instruments. Unfortunately, this approach tended to create latencies that complicated the coordination of signal source and measurement functions.

Depending on the instruments and how well they were integrated, it could also place limitations on how short the pulses and their duty cycle could be. Despite these limitations, users of these earlier pulsed I-V test systems soon began applying them to a variety of other characterization tasks, including non-volatile memory testing, ultrafast NBTI reliability testing, and many other applications.

Given their somewhat limited dynamic range, these systems remained something of a specialty technology. In order to become a mainstream test technology, the next generation of ultra-fast I-V testing systems would have to provide a very broad source and measure dynamic range. That meant they had to be able to source sufficient voltage to characterize flash memory devices, as well as voltages low enough to handle the latest CMOS processes.

For example, consider an embedded flash device in a CMOS process—the flash device might require up to 40V to program, but the CMOS process is running on 2.5V, so the test system used must be able to supply voltages for both requirements. It also needed to have a broad enough current range to handle the newest technologies, and fast enough rise times and long enough pulse widths to cover a wide range of applications. It had to be simple to use, and have an interconnect system that would allow the system to deliver accurate results reliably.

The New Generation of Parameter Analyzers. Semiconductor parameter analyzers have evolved to solve many of these test problems. Now it’s possible to find test systems that combine DC I-V, C-V, and ultra-fast pulse I-V test capabilities. For example, in the Keithley Model 4200-SCS system, the Model 4225-PMU Ultra-Fast I-V Module has been added to the DC I-V and C-V measurement modules. Thus, all three required measurement types can be integrated in a single test system that’s optimized for advanced applications such as:

Flash, PCRAM, and other nonvolatile memory tests
Isothermal testing of medium-sized power devices
Materials research testing for scaled CMOS, such as high-k dielectrics
NBTI/PBTI reliability tests
LDMOS testing
Testing of III-V materials and devices such as GaAs

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Naturally, the computerized operating system and test library of an integrated test system of this type must make it easy handle a broad range of test protocols, and quickly switch between the three different types of test. An example of this is the Keithley Test Environment Interactive (KTEI) operating software, which provides a single test environment that allows a user to combine measurements made with different instrument types into a single test sequence.

By using plug-in modules for the hardware chassis in a parameter analyzer, the test system can be readily optimized to address specific applications or sets of applications. Just as important, as new applications come along, a modular architecture allows for cost-effective system upgrades. For instance, in the Model 4200-SCS system, builders can choose from medium- and high-power Source-Measure Units for DC I-V measurements, an optional capacitance meter for C-V measurements, and an ultra-fast (pulsed) I-V module for high-speed pulse measurements.

Thus, the latest generation of parameter analyzers offers users a complete solution for an application like charge pumping, because the test system can be configured for the ultra-fast pulse generation and sensitive DC current measurements required. The test libraries include predefined tests for making most of the common charge pumping measurements, such as a pulsed base voltage sweep or a pulsed voltage amplitude sweep. In the case of solar cell testing, integrated I-V and C-V measurement capabilities make it possible to perform a wide range of measurements, including capacitance-frequency (C-f), drive level capacitance profiling (DLCP), four-probe resistivity (?, ?), and Hall voltage (VH). In addition, the software automates the measurements and provides results analysis.

Pushing the Limits of Instrumentation. While it’s important for a test system to handle the day-to-day measurements of modern devices and materials, the development of leading edge technology often demands more. This makes parameter analyzers with open system architectures even more important. To address the needs of advanced technologies, Keithley’s Model 4200-SCS allows users to modify any of the measurements in its test libraries, such as C-V, C-t, and C-f measurements. This opens the door for more customized testing and analysis, such as that needed for solar cells; high- and low-k structures; MOSFETs; BJTs; diodes; III-V compound devices; carbon nanotube (CNT) devices; doping profiles, TOX, and carrier lifetime tests; as well as junction, pin-to-pin, and interconnect capacitance measurements.

System speed and hardware flexibility are equally important, including the ability to add external instrumentation without sacrificing throughput and measurement performance. Many of the new ultra-fast I-V tests that lab users wish to perform, such as charge pumping and NBTI testing, may require greater current sensitivity than a standard instrument module provides (e.g., the Keithley Model 4225-PMU). This may require the addition of an external preamp.

For such an application, the optional Model 4225-RPM Remote Amplifier/Switch for Keithley’s parameter analyzer offers additional low current ranges that extend the system’s current sensitivity down to tens of picoamps. It also reduces cable capacitance effects and supports automatic switching as needed between the system’s ultra-fast pulse module, C-V module, and SMU modules to perform different types of testing on the fly. There is no need to disconnect a module’s wiring then reconnect it to a different instrument. These features reduce test system latencies and help improve throughput.

Older parameter analyzers typically were designed for specific types of test within the current-sensitivity/measurement-time application space, such as ultra-fast (UF) NBTI in statistical process control testing (SPCT), and even higher speeds in PCRAM testing. The traditional DC I-V SMU can source and measure currents up to about 1A and down to about a picoamp. Although adding a remote preamplifier allows resolving signals as low as 0.1fA, the best speed is about 10 milliseconds. In contrast, the Keithley Model 4225-PMU ultra-fast I-V module allows making a measurement in as little 10ns, which is critical for characterizing device recovery. Its optional remote amplifier/switch extends the current resolution of the module down to tens of picoamps, just slightly above the limit established by the Johnson noise produced by devices under test.

Part III of this 3-part article will discuss cabling considerations for different types of testing. This can be just as important as instrument capabilities in achieving the optimum throughput and signal integrity.

Lee Stauffer – About the Author:

Lee Stauffer is the Senior Staff Technologist for Keithley Instruments’ Semiconductor Measurements Group, based in Cleveland, Ohio. Prior to joining Keithley, his career included designing satellite communication systems, as well as equipment and product engineering in semiconductor fabs. Keithley designs, develops, manufactures and markets complex electronic instruments and systems geared to the specialized needs of electronics manufacturers for high-performance production testing, process monitoring, product development and research.

Source: http://www.articlesbase.com/technology-articles/evolution-of-semiconductor-parameter-analyzers-for-three-critical-types-of-semiconductor-measurement-part-ii-2823418.html

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Article Tags:
ac impedance, cabling, capacitance meter, capacitance voltage, carbon nanotube, carrier lifetime, c f sweep, charge pumping, cmos

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