Testing for defects oriented nanometer CMOS VLSI

Posted on August 9, 2010, 7:03 pm

process tolerances DescriptionFailures technology products with nano-metric for failure and reduced to give rise to significant challenges for IC testing. As the variation of basic parameters such as channel length, threshold voltage, the thin oxide thickness and interconnect dimensions is well beyond acceptable limits, new test methods and a deeper understanding of physics Vice-fault mappings are needed. Testing for defect oriented nanometer CMOS VLSI C.. . More>>

Testing for defects oriented nanometer CMOS VLSI