Free Intellectual Properties

PopCorn - 1 Updated 3/00

• EDA platform : ispADVANCED
• design type : Synplicity Verilog

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Editorial:

In this time of Giga-Herz performance processors, one tends to shy away from anything that is not hundreds of Megaherzs in clock speed. But gauging a processor simply by the clock speed is one thing, and appretiating it from the internal architecture is quite another. In order to do the latter one typically needs to know intimately the concepts and architectures which are the pillars of supescalar pipeline RISC processors of today.

When was the last time when you could say "I know how this processor works from inside and out. I know all of its sequencing, and I know how to add more instructions and how to make it run faster and how to scale it" When was the last time when your project needed a processor and you quite could not find the perct one, but ended up using whatever was available. Did you not which you could ahve used a processor of your own design ? PopCorn is an elegant processor ideal for real-time applications. It is small yet sleek. Check it out !

 Description

• The updated version (3/00) compiles correctly under Altera, Lattice and Xilinx platforms. If you'd like to receive the project design directory please specify your platform and fill the feedback form. Xilinx users do not forget to enable ifdef support under synthesis/option.
• As the name suggests, this a very straightforward 8 bit microprocessor. The featureset of the architecture has been purposely minimized so that the resuting design can be fitted into one popular CPLD currently in the market such as : Lattice isp3256, Xilinx 3030 and Altera Max 7256.
• This microprocessor design supports 25 instructions and 3 addressing modes (register direct, immediate and direct (to memory) ). An instruction can be from 1 byte (opcode only) upto 3 bytes in length. An internal stack pointer allows a stack to be as deep as the external memory provided (current IP upto 4Kbytes).
• An 8 bit bidirectional port is also included in the design to facilitate peripheral communication.

Documentation

The following file describes the design in much more detail: popcorn_spec.pdf

PopCorn-V3 spec availalbe here.

Design Files

There are several design files

The Original PopCorn

popcorn.zip updated on 3/00	There are 3 verilog files here. It is pretty much self commented pc.v popcorn.v sequencer.v	pkzipped
popcorn_pin.pin	Pin-out of the Lattice isp3256 CPLD i've used to proto.
popcorn_edif.zip	EDIF file
popcorn_isp3256.zip	JEDEC fusemap for the Lattice isp3256 CPLD.

PopCorn-V3

Download Verilog Files here.

For users of Verilog-XL, ModelSim, VCS, NC-Verilog, or other HDL Simulator

Download PopCorn-V3 8bit microprocessor with Verilog Testbench, running code.

Assembler

• No home-grown micro is fun to use without a decent assembler. I've attempted to write a slick assembler but it's stil a long way till then. What I've got so far is halfway decent. The assembler is table-driven type. That is, the opcode and instruction labels are not hard coded, but are read-in as a file. This allows the assembler to be reconfigured easily.
• The assembler generates a hex image dump of the assembled source code. You need to load it as 'hex' from your eprom/flash burner, instead of intel-hex. format.
• pcasm.zip
• There are a couple of files in the above, the source code, the executable and the latest opcode table. No documentation yet.

Test Codes

To see if you actually compiled the verilog files correctly and the design is working properly, try these sample codes:

portio.asm	counts up from 0 to F.
timer.asm	counts up from 00 to FF then wraps around in the port IO.

Besides these, I have intentions of writing other useful codes such as multiply, divide, and other math routines, as well as other functions. Stay tuned.

Picture of Prototype

Click here to see Popcorn prototype running a test code