Analog Rails To Release IC Design Environment August 31, 2008

Analog Rails Simulation Environment

Chandler, AZ (PRWEB) August 13, 2008

Analog Rails will release a IC Design environment on August 31, 2008. Analog Rails(TM) is a complete semi-automatic IC design environment targeting the entire analog circuit design flow. It is the most automated solution in the “custom” IC industry. Along with unified, correct by construction schematic and layout, Analog Rails features automatic layout, which includes an automatic placer, router, parameterized cells, and differential structures. Additionally, Analog Rails also incorporates a complete simulation environment. Layouts are assisted by real-time DRC and LVS aware functionality, which allows Analog Rails the unique approach of porting real parasitics. This enables the user to simulate with real layout values instead of estimations, which is the current industry standard. A free spice simulator is included so that the user can launch as many simulation runs as necessary for the built-in optimizer without requiring third party simulator licenses.

The release of this expert analog design system represents a new methodology based on inputs from leading designers in the industry. By simplifying analog design methodology via the combination of automated and semi-automatic approaches, Analog Rails addresses analog design challenges for next generation designs.

Steven Klass of Standard Microsystems had this to say in an article posted on his blog about Analog Rails: “This tool represents a clear methodology shift… The demise of the block level analog layout engineer. Why? First as I said earlier, the layout automation piece is very intuitive and friendly. Plus the smaller technology geometries that analog design is pushing into (less than 90nm) is forcing simulation earlier (using Cadence) to account for device parasitics (LOD). So the analog engineer is already doing a fair amount of the placement and letting the layout guy clean up the work. But this tool is correct by construction and so the layout is clean from the get-go. So involving a layout person to ‘clean it up’ isn’t necessary.”

Pirooz Hojabri, co-founder and VP of Engineering at Plato Networks, had this to say: “Utilizing the high ft of sub-micron CMOS has opened a new paradigm in circuit design and to reduce the product cycle time, there is a need to understand the parasitics early in development process. Analog Rails has taken a critical step in this direction.”

And Mike Kappes, CEO of IQanalog, said that “what Analog Rails is developing is a tool that will enable circuit designers to extend their deliverable from annotated schematics to finished and polished layout without outside layout or CAD involvement. Furthermore, having a tight coupling of schematics and layout design will result in better design practices with fewer extraction iterations.”

Analog Rails has been natively developed upon the new industry standard database, OpenAccess, which allows customers to seamlessly adopt individual tools or a whole flow. It also allows seamless design exchange between tools and partners supporting OpenAccess. OpenAccess has been widely accepted by leading EDA vendors such as Cadence, Synopsys, Mentor, Magma, and Silicon Canvas.

Free, 24/7 PDK support is included with every Analog Rails license purchase. Pricing, contacts, and specific details about Analog Rails (including online video demos), can be found at the company’s website, http://www.analograils.com.

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