Introduction The word of the chip design is to build an integrated chip, by integrating billions of transistors to achieve an application. An application can be favorable, a specific requirement such as microprocessors, routers, cell phones, etc. An integrated circuit designed for a specific application is known as ASIC Application (Specific Integrated Circuits). Today’s ASIC Chips prettly complex is packed with larger pieces of transistors for a specific manufacturing process for the manufacture of integrated circuits in a sub nanometer regime, involving many, many challenges, such as knowledge of various protocols, architectures, models, formats, standards, knowledge of logic CMOS Digital Design Concepts, tame the EDA tool for the region as the requirement of differential design, timing, power, temperature, noise, routability, lithography knowledge, knowledge of variability such as different channel length, Vt, variations in line width, lens abrreations, the effects of IR drop, inter-die, intra-die variation, effects and various combinations of sound effects such as noise package, EMI noise, grid noise, noise Cross talk and his ability to test and validate and learn to model and characterize all these effects at the initial stage of the design phase, measures to increase the yield curve to increase profitability, with a short time-to-market to minimize risk and maximize the predictability and a modular approach to success. Now we dwelve yourself to art “Chip Design” Used a lot of technical jargon, no fear, we will soon. . . Be with me promise you understand the concepts behind Chip Desiging. Before designing a chip? Need Brain Storm 1. What the chip market is expected? 2. What are the protocols involved in the chip? 3. What will be our manufacturing / Architecutes Bus? 4. what is the power / IR-drop / time / area / performance / targets and how the budget of the chip? 5. What is the process in which the chip will be built? 7. what are the third different requirements Memory IP /? 8. This is our design flow and EDA tools and methodology in question? 9. What is the estimated cost smart? 10. Above the bottom line of any business model is money, this will be our profit model, estimation of our ROI (Return on Investment). For concepts Chip Desiging, free! Www. vlsichipdesign. comAnalogy Chip Design Architecture Building Vs Why an analogy with the building’s architecture, it is fair to understand the concepts Chip desiging a better way, as we are very familiar with the architecture of the building, then it will be easy for us to chip Architecture Design. VLSI (Very large scale integration) flow has evolved similar to the flow involved in construction. Now, let us dwelve in the flow of construction in order to better understand the design of VLSI chip development cycle. Whenever we begin to construct a building, we have an architecture, how the building should look like, looks outside and all, like the one we will develop an architecture of the chip-design, based on the requirement the product, the product is sent to and used that needs the specification itself, whose modules. Lets go to the party implementation of both the building and Chip. We first came with the floor plan of the building, and we come with the floorplan of the chip, based on connectivity / accessibility / vaasthu we place our rooms, so we have the constraints place the blocks. As we build the brick building for Chip Design, we have libraries, which are like pre-designed blocks for a specific functionality. Now try to understand the power structure or power connectivity in our building. Initially, we plan our building’s electrical, we have a requirement that all our electrical needs to get power. Similar to that we need a smart power, the power required is supplied by the power pads on a ring topology as to have a uniform distribution in all corners of the chip and supply must reach all standard cells (bricks to-Chip Design). It is called as power network topology in Chip-Design, now the requirement is how we design our Power-grid to reduce IR-drop, so that our level of requirement of obtaining cells ‘adequate food. I would not do justice if I did not participate in discussions on the clock and clock-tree in the Chip-Design Flow. We synchronous design and the asynchronous design (hard to verify). The majority of the bulleted follow synchronously coding, for which Static Timing Analysis is possible. For the relevance of flops the clock to those flops should be at the same time from the crystal with an angle with certain objectives in the chip. To do this, a stage known as a clock-tree is performed after power grid is created. Try to visualize the concept behind Place & Route in Chip Design. We need to undergo many modeling concepts, understand the process of design-CHIP. To get a better understanding of the concept of place and route, we assume a society where people who speak different languages are alive, and let us imagine that people speak the same language live in a community, then communication is much easier, even in the so-piece design, standard cells that have the field of ship design, are placed closer to the stream of investment of this concept is known as regioning. Now, in the regioning, groups of standard cells, cells that are actually sharing data, placed close by so there timing is well done and optimized. This step is called placement, connectivity between the standard cell is known as the routing, the challenge is to be optimized and reduced wire length. Let us now try to understand the concept behind the signal integrity in chip-design, we have often wondered IF Effect. As the process is narrowing day by day, and our silicon realestate is expensive, we try to accommodate more and more standard-cells in the limited area, so that the cells are placed in very close proximity, so the transition from one can have an impact on the behavior of others, which may make the journey to be faster or slower, this number is known as signal integrity. So alike in our construction to maintain integrity in the house (near the zone), in the limited area of modurality, we try to create fences, around buildings, so one can think of a concept Shielding known as the net of high frequency signal with the power running through the nets. We make the spacing between buildings, the same way we can make the spacing between the nets, which are in close proximity. To validate the silicon manufacturability issues, the concept in Desigining Chip is design for test (DFT). One technique of DFT is scan-chain. To understand the concept of the chain analysis, we can see that we have a first entry door and a door emergency exit, and a person moves from the entrance and exits from the rear exit door of the building that we are sure that there is no blockage in the rooms in the building, to make that person stuck like this analogy, the flip-flops are connected in-creation seems ‘channel scan and test input values are transmitted from the digital input channel of the chip and the expected data is displayed in the scan-chain output of the chip, then the assumption is the chip is free of problems in manufacturability as stuck faults (stuck at one or stuck at zero). For concepts Chip Desiging, free! Www. vlsichipdesign. com