Abolition of the frequency multi-core will rewrite the myth of the law MoorePas difficult to see multi-core processor is the processor, an inevitable trend. The mobile and embedded applications, desktop applications or server applications, multi-use architecture core.la processor technology is multi-core development inévitableLes 20 years microprocessor performance to promote continuous improvement are two main alternatives IBM ThinkPad X40 laptop battery factors: the rapid advances in process technology semiconductor and architecture of continuous development. process technology semiconductor research progress in microprocessor architecture has raised new questions, opens new space, architecture Jinzhan you in the technological development of semiconductor process based on microprocessor performance improved. These two factors interact and promote each other. In general, the process and circuit technology enables processor performance has increased 20 times, the architecture allows the development of higher performance processor 4 times, the technology allows the compilation of processor performance about 1. 4 times. But today, the patterns are difficult to maintain. The emergence of development of multi-core technology and applications of the natural product. This is mainly based on the following facts: 1. coming era billion transistorsConformément to Moore’s Law, the speed of microprocessors and integrated single chip doubles every 18 months. After years of development, the main frequency of general purpose microprocessors have broken 4GHz, also reached a width of 64-bit data. In the manufacturing process is also at an alarming rate in developing, 0. 13um microprocessor technology in volume production, the 90nm process after the next generation of microprocessors is released. If it continues to 2010, the number of transistors on a chip integration will be more than one billion. Therefore, the architecture of the study also encountered a new problem: how to effectively use a large number of transistors? The international community the question of influence. multi-core chip by a number of simple hearts enjoy these transistors resources, maximize the potential effectiveness énergétique.2. gate delay is gradually reduced, while the overall interconnection delay has been on augmentationAvec development of VLSI technology, reducing the characteristic size of the transistor, thus reducing the gate delay of the transistor, the interconnect delay, but it is becoming increasingly important. When the chip manufacturing process to 0. 18 microns and even more hours behind the gate delay line, a limit of the main factors to improve the performance of the circuit. In this case, as CMP (single-chip multi-processors) distributed architecture Zhong signal the less overall, and Jizhong Shi structure as the structure, superscalar processors, in Kefu Xian You Shi Yan Chi affect Fangmian over.3. Rules consistent with rules PollackSelon Pollack, we know that the CPU performance increases directly proportional to the battery Dell Inspiron 9300 the square root of its complexity. If the hardware logic processor can increase performance dual 40%, and if the use of two simple identical processors to form a dual-core processor, the size of the equipment, then get 70 ~ 80%% increase performance. Year in the region while rétrécissant.4. Increased consumption énergieAvec development of technology and increasing complexity in chip, chip heat is becoming more important. The multi-core processors in a single nucleus slower processors consume less energy, produce less heat. Meanwhile, single-core processors to increase the original transistor can be used in multi-core processors to increase nuclear generation. To meet the performance requirements based on multi-core processors by disabling (or reduction in frequency) processor technology for low power, can effectively reduce energy consumption .5. Design considerations coûtAvec processor architectural complexity increases, and rising labor costs, design cost is linear with time even superlinear growth. The multi-core processors, such as processor IP reuse, the design can greatly reduce the cost. At the same time the module validation inférieur.6 cost significantly. Architecture inévitableSuperscalaire (superscalar) structure and very long instruction word (VLIW) in the current structure of high-performance microprocessors are widely used. But they have seen the development of insurmountable obstacles. superscalar structure with multiple functions simultaneously execute multiple instructions to complete the instruction level parallelism (Instruction-Level Parallelism, ILP). However, the complexity of its control logic to realize the difficulties, the research shows that ILP superscalar structure is generally not more than 8. VLIW structure, the implementation of several identical features a long investigation, but there are two major problems: compiler support and compatibility binaire.L future consumer applications require more processing with simultaneous instruction capacity, LG R405 battery but not from a single thread may already be extracted more parallelism, especially in the two following reasons: First, by increasing the chip area increases the cost of production, secondly, the design and verification of time spent more time. In the current processor architecture, the more complicated the design can be improved performance limitées.La dependence on a single wire limits the majority of applications can be extracted from the parallelism, and commercial applications general public, as database OLTP (Online Transaction Database) and Web services (like Web server), etc., are generally more thread-level parallelism (TLP, Thread Level Parallelism). To this end, researchers presented two new architectures: a single chip multi-processor (CMP) and Simultaneous Multithreading Processor (Simultaneous multithreading, SMT), these two architectures can take advantage of these applications and the parallel instruction in the Wire level parallelism, and thus significantly improve the performance of these applications.D an architectural standpoint, SMT CMP CPU utilization superior, to overcome the impact of benefits over time. CMP is also the biggest advantage of the MTS over the simplicity of its modular design. Very easy to copy a simple design, instruction scheduling and simpler. GTS in multiple threads simultaneously on a shared resource contention will affect their performance, while CMP thesis on shared resources is much less so when demand is high thread-level parallelism, the CMP performance generally better than the GTS. In addition, the design, more short than long CMP chip connection to the centralized design of the head SMT easier to improve the operating frequency of the chips, which to some extent, play an optimization results of performances.En Briefly, the chip multi-processor, single-chip base of more than a microprocessor to increase the parallelism of the program. Each processor core is essentially a relatively simple or relatively simple single-threaded microprocessors multi-threaded microprocessors, multiple microprocessors that can be parallel to the implementation of the code base, so they have more thread-level parallelism. Since CMP is a relatively simple microprocessor used as the heart of the processor, which CMP at high frequency, design and verification of short cycle, the control logic is simple, scalable and easy implementation, low power consumption and communication with low latency. In addition, CMP can take full advantage of the different applications of parallelism at the instruction level parallelism and thread, high thread-level parallelism in applications such as commercial applications can take advantage of this structure to improve performance Toshiba PA3383U-1BRS Battery. The current architecture single-chip multi-processor has become a processor of an important trend in development.