Posts Tagged ‘Technologies’

Reverse Graded Buffers for CMOS Technologies: Reverse Graded High Content (x>0.75) Si(1-x)Ge(x) Virtual Substrates

Sunday, October 16th, 2011

Reverse Graded Buffers for CMOS Technologies: Reverse Graded High Content (x>0.75) Si(1-x)Ge(x) Virtual Substrates

Moore?s law suggests that the number of transistors which can be economically fabricated on a chip exponentially increases with time, traditionally this has been done by simple scaling of the channel within metal oxide semiconductor field effect transistors (MOSFETs). However, this approach is fast reaching fundamental limitations, which necessitates the substitution of different materials in traditional silicon devices to enhance their performance. A high composition (x>0.75) Si1-xGex alloy layer can be used as a buffer layer for such materials. However, buffers normally consist of a trade-off between structural quality factors and the physical attributes of any active channel layer are directly affected by those of the buffer which must not compromise device performance. In this work, a good quality high Ge composition SiGe buffer is investigated and is compared to more popular buffer fabrication techniques. All aspects from epitaxial growth to structural characterisation are explained from basic principles and should be useful for anyone in the semiconductor industry to gain a grasp of structural analysis which is typical for this field of research.

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Analog CMOS low power for pacemakers: design and optimization of bulk and SOI Technologies

Friday, August 13th, 2010

Product DescriptionPower reduction is a key priority for battery implantable medical devices, especially pacemakers, however long battery life or increase the size using a smaller battery. Low Power Analog CMOS for pacemakers proposes new techniques for reducing energy consumption in analog integrated circuits. Our main example is the pacemaker sense channel, which is representative of a broad class of circuits to biomedical qualitative. . . More>>

Analog CMOS low power for pacemakers: design and optimization of bulk and SOI Technologies

Reverse graded buffer CMOS technologies: Reverse Graded high in virtual substrates

Sunday, July 25th, 2010

DescriptionMoore product? The law suggests that the number of transistors that can be economically fabricated on a chip increases exponentially over time, traditionally this was done by simple scaling of the transistor channel in metal-oxide semiconductor field effect (MOSFET). However, this approach is quickly reached fundamental limits, requiring the replacement of various materials in traditional silicon devices to improve their performance. High. . . More>>

Reverse graded buffer CMOS technologies: Reverse Graded high in virtual substrates

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Design Process-Aware SRAM and test

Tuesday, May 4th, 2010

scales of technology products in the region descriptiones nanometers, design and testing of Static Random Access Memories (SRAMs) becomes a very complex task. disturbance processes and mechanisms of various defects contribute to the increased number of unstable SRAM cells with parametric sensitivity. increasing size of networks increase the likelihood of SRAM cells with marginal stability and pose strict constraints on transistor parameters distributions. Standard functional tests often fail to det. . . More>>

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Design Process-Aware SRAM and test

Variation Aware and analog circuit design mixed-signal CMOS technologies in the new Multi-Gate

Tuesday, April 27th, 2010

Product DescriptionSince scale CMOS is reaching the area of nanometer serious limitations force the introduction of new materials, concepts and architectures of peripheral devices. multi-gate devices using gate dielectrics with high permittivity are considered a promising solution to overcome these limitations of conventional bulk planar CMOS scaling. Variation Aware analog and mixed signal circuit design in emerging technologies Multi-Gate CMOS technology provides an assessment based on analog a. . . More>>

Variation Aware and analog circuit design mixed-signal CMOS technologies in the new Multi-Gate

Reliability Wearout Mechanisms in Advanced CMOS Technologies

Tuesday, April 20th, 2010

  • ISBN13: 9780471731726
  • Condition: NEW
  • Notes: Brand New from Publisher. No Remainder Mark.

Product DescriptionA comprehensive treatment of all aspects of CMOS reliability wearout mechanisms This book covers everything students and professionals need to know about CMOS reliability wearout mechanisms, from basic concepts to the tools necessary to conduct reliability tests and analyze the results. It is the first book of its kind to bring together the pertinent physics, equations, and procedures for CMOS technology reliability in one place. Divided into six relat. . . More >>

Reliability Wearout Mechanisms in Advanced CMOS Technologies

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test

Monday, April 19th, 2010

Product DescriptionAs technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays increase the likelihood of cells with marginal stability and pose strict constraints on transistor parameters distributions. Standard functional tests often fail to det. . . More >>

CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test

ESD Protection Device and Circuit Design for Advanced CMOS Technologies

Saturday, April 17th, 2010

Product DescriptionESD Protection Device and Circuit Design for Advanced CMOS Technologies is intended for practicing engineers working in the areas of circuit design, VLSI reliability and testing domains. As the problems associated with ESD failures and yield losses become significant in the modern semiconductor industry, the demand for graduates with a basic knowledge of ESD is also increasing. Today, there is a significant demand to educate the circuits design and reliability teams. . . More >>

ESD Protection Device and Circuit Design for Advanced CMOS Technologies

Low Power Analog CMOS for pacemakers: Design and Optimization in Bulk and SOI Technologies

Tuesday, March 30th, 2010

DescriptionPower reduction product is a key priority of piles of implantable medical devices, including pacemakers, or life of the battery to increase or decrease the size using a smaller battery. Low Power Analog CMOS for pacemakers proposes new techniques for reducing energy consumption in analog integrated circuits. Our main example is the chain direction pacemaker, which is representative of a wider class of circuits to biomedical quality. . . More>>

Low Power Analog CMOS for pacemakers: Design and Optimization in Bulk and SOI Technologies

CMOS SRAM Circuit Design and Parametric Test Nano-Scaled Technologies: Process-Aware SRAM Design and Test

Sunday, March 21st, 2010

Product descriptiones technology scales into nano-meter region, design and testing of Static Random Access Memories (SRAMs) becomes a very complex task. Disturbance processes and mechanisms of various defects contribute to the increased number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays increase the probability of cells with marginal stability and pose strict constraints on transistor parameters distributions. Standard functional tests often fail to det. . . More>>

CMOS SRAM Circuit Design and Parametric Test Nano-Scaled Technologies: Process-Aware SRAM Design and Test